1. Field of the Invention
The present invention relates to semiconductor memory devices and more specifically, to a pseudo-differential sense amplifier for reading memory cells.
2. Description of the Related Art
Sense amplifiers are used to detect small differential signals generated by memory cells and to shift the voltage levels of the memory cell output signals to a magnitude compatible with output circuitry in a memory chip. One type of integrated circuit memory, that can be connected to a sense amplifier, is the erasable programmable read-only memory ("EPROM"). EPROMs frequently use memory cells that have electrically isolated gates (floating gates) such as an enhancement-type n-channel metal-oxide semiconductor field effect transistor (MOSFET) with two gates made of polysilicon material, otherwise known as FAMOS (Floating Gate Avalanche Injection Metal Oxide Semiconductor device). In FAMOS technology, information is stored in the memory cells in the form of charge on the floating gates. Such memory cells are programmed by placing a charge on the floating gates. The EPROM can be programmed by a user, and once programmed, the EPROM retains its data until erased.
The EPROM comprises memory cells logically organized by an array of rows and columns. Typically, the rows represent word lines and the columns represent bit lines. By selecting the appropriate word line and bit line, each individual cell may be programmed or read. During the programming operation a given memory cell or cells are selected for programming, then a voltage is applied to the control gate of each memory device (e.g. a FAMOS device). A programming voltage is applied to the bit line of each selected memory cell. The programming voltage generates a programming current flowing through the selected bit line, thus programming the memory cell or cells. The FAMOS memory cell, thus, can be in a programmed state, the memory cell not conducting current or in a "not programmed" state, the cell conducting current.
Memory cell sizes and the corresponding memory cell output current is reduced as array density is increased to maintain cost effectiveness. As a result, sense amplifiers are required to be very sensitive to small current changes coming from the memory cells. Increased transistor density causes a reduction in speed and memory cell output current. That is, increased transistor density entails larger resistors and capacitors distributed among the rows and columns of the cell matrix of the device, which in turn increases the RC time constants. Increased RC time constants and reduced memory cell output current result in slower device speeds. There are at least two particular factors which limit the speed of the device. One of these factors is the delay related to the RC time constant of the row in the cell matrix--R being the resistance of the polysilicon conductor, and C the capacitance of the gates of the cells connected in parallel to the row. Another factor is the delay related to the capacitance of the column in the cell matrix, i.e., of the drain junctions of the connected cells and amount of memory cell output current necessary to charge the column.
In pseudo-differential sense amplifiers the speed can also be affected by a noise event at the V.sub.CC supply voltage or at the V.sub.SS supply voltage. More specifically, a delay in the response of the sense amplifier can be caused during a glitch to the V.sub.SS or V.sub.CC supply, one of the supply voltages, V.sub.SS or V.sub.CC, failing to follow a change in the other supply voltage. If a noise event, affecting V.sub.SS or V.sub.CC, occurs during a sense amplifier transition, a speed push out will be experienced. A speed push-out can be defined as a delay in the response of the sense amplifier and the reasons for its occurrence can be understood in conjunction with FIG. 1.
FIG. 1 illustrates a conventional pseudo-differential sense amplifier including differential stage 2 having two inputs (4, 6) and one output 8, an array path 10, and a reference path 12. The array path 10 is connected to the array load device M.sub.1 via an array node IN. In the particular configuration illustrated in FIG. 1, transistor M1 is an N-MOS transistor having the gate and the drain connected to the supply voltage V.sub.CC, and the source connected to the array node IN which is connected to the input 6 of the differential stage amplifier 2. The differential stage is cascoded to the output of cascode transistor M.sub.CA which is connected to the array node IN of the array path 10. The cascode transistor M.sub.CA, in this particular configuration illustrated in FIG. 1, is an N-MOS transistor having the drain connected to the array node IN, the gate connected to a cascode reference voltage 18, and the source connected to the node DRA. Furthermore, an array memory cell MRA is connected to the bit line array node BLA via a bit line 20. A bit line data signal is fed to the array node IN via the bit line 20, the bit line array node BLA, the column decode transistor M.sub.CDA and the cascode transistor M.sub.CA. The above-described configuration of the array path connected to the array load device and to the array memory cell provides an input signal to the array node IN. Similarly, a reference signal is generated through a reference path 12 at the reference node REF, as it will be explained in the following paragraph. The differential stage 2 receives the array input signal and the reference input signal, and generates in response sense amplifier output signal OUT. Differential stage 2 includes P-MOS transistors M.sub.CM1 and M.sub.CM2 connected in a current mirror configuration. M.sub.CM1 is coupled at its drain to the drain of transistor M.sub.D1, while M.sub.CM2 is coupled at its drain to the drain of transistor M.sub.D2. The sources of transistors MD .sub.2 and MD.sub.1 are connected to current source transistor M.sub.CS which is an N-MOS transistor in this particular example.
With respect to the reference path 12, this path and the array path are, generally, symmetrically designed from the cascode device down to improve process compensation and noise immunity. The reference path includes the reference load device M.sub.2 having a channel width 2W, substantially double the width of the channel of the array load device M.sub.1. Consequently, the impedance of the reference load device is substantially half the impedance of the array load device. The reference load device M.sub.2, in the particular embodiment illustrated in FIG. 1, is an N-MOS transistor having the gate and the drain connected to V.sub.CC and the source connected to a reference node REF. The reference node REF 16 is coupled to the second input 4 to the differential stage 2. This input is connected to the gate of transistor MD.sub.1 of the differential stage 2. The reference path further includes a cascode reference transistor M.sub.CR having the drain connected to the reference node, the gate connected to a cascode reference voltage 18 and the source connected to the node DRR. Furthermore, the node DRR is connected via transistor M.sub.CDR, the node BLR, and a dummy bit line of the dummy memory cell, to a dummy memory cell MRR constructed similarly to the array memory cell. Finally, reference dummy cell MRR is connected to a voltage supply source V.sub.SS. A reference signal is, thus, generated at the node REF connected to the second input 4 of the differential stage 2. A high voltage level is seen at array node IN when reading a programmed cell, while a low voltage level is seen when reading a "not programmed" cell. The sizes of the load devices M1 and M2 are chosen such that the reference voltage REF falls in between the high and the low voltage level of the array node IN.
The prior art pseudo-differential sense amplifier illustrated in FIG. 1, is designed so that the reference path matches the array path as close as possible, in order to maximize process compensation, noise margin, speed balancing, etc. A competing consideration in designing a pseudo-differential sense amplifier is centering the reference voltage between the high and the low voltages of the array path. To achieve such design one has to give up current gain on the reference side by making the reference load device of the reference path less resistive. This can be seen in FIG. 1 which shows a reference load device M2 with a channel having a width 2W as opposed to the width W of the array load device. The consequence of this design is that a less resistive reference load device causes less current gain on the reference path. A noisy event that causes a current change in both the array and reference paths will, thus, affect the array path more than the reference path.
As explained above, a common occurrence of a noise event affecting the performance of the sense amplifier, takes place during a noise event to the V.sub.SS supply or the V.sub.CC supply. In this case, the asymmetric distribution of resistive elements in the array and reference paths, due mostly to the asymmetrical load devices, will cause the reference node to track more closely to the V.sub.CC supply voltage since this reference path is more tightly coupled to V.sub.CC. By contrast, a noise-event at V.sub.SS will affect the array node more than the reference node. Consequently, if a noise event occurs during a sense amplifier transition, a speed push-out will be experienced due to the fact that the "IN" voltage and the "REF" voltage signals will not follow each other closely, as in the absence of noise, or as in the case where the array and reference load devices would be symmetrically designed.
With respect to the memory cell, when the memory cell is in a "not programmed" state, cell current flows through the array path, thereby causing the voltage seen at the node IN to be at a low level. A cell having a programmed stale, however, will prevent current from flowing, thereby causing the voltage seen at the IN node to be at a high level. Consequently, the IN node will have a low or a high voltage value. Because symmetry is required to achieve process compensation and noise immunity, a dummy reference cell, or the equivalent parasitic components, is/are required in the reference path. However, since the reference cell cannot be turned on halfway, in order to achieve the centering of the reference voltage, the dummy cell will have to fully conduct. To complicate things more, if the loads used in the reference and the array paths had the same impedance, one could not get a differential sensing considering the substantial symmetrical configuration of the array and reference paths.
The design of prior art sense-amplifiers suffers of flaws with regard to noise events due to the difference in the impedances of the loads. For example, by having a less resistive reference load device, the reference node REF will be more tightly coupled to V.sub.CC as opposed to the array node IN which is separated from V.sub.CC by a higher resistance. Moreover, a noise event at V.sub.CC or V.sub.SS will be translated into a current change in the array and reference paths. Such current change in turn will cause a change in signal, i.e., voltage at both the array and reference nodes. However, the change in signal at these nodes will be different due to the differences in the impedances of M1 and M2. For example, an increase in both currents will cause a larger voltage drop across the array path than across the reference path causing, thus, the array node voltage to drop more than the reference node voltage. As explained above, the reason is that a change in current in the reference path is not going to pull down the REF node as much as the current change would pull down the IN node in the array path because M2 is less resistive than M1. In sum, due to the asymmetrical design of the load devices, two contradictory events related to the noise are happening: the reference path couples more to V.sub.CC and less to V.sub.SS ; the array path will couple less to V.sub.CC and more to V.sub.SS.
FIG. 2 illustrates a wave form diagram showing the effect of noise upon the output signal of the prior art sense amplifier. The diagram 2-1 of FIG. 2 illustrates the input IN and reference REF wave form signals to the differential stage and the output signal OUT of the sense amplifier in the absence of noise. As one can see, the reference signal tracks the array signal, the difference between these signals remaining stable. Upon a change of address illustrated in FIG. 2 by the wave form A's abrupt descent, the array node voltage rises up and crosses the reference signal causing a sense amplifier transition. Before the transition, the array signal is lower than the reference signal, and the sense amplifier output signal is high. When the array voltage signal rises above the reference signal, the sense output signal transitions from high to low.
FIG. 2--2 shows the same prior art wave form diagram, at the same time scale, with the exception that in this case, noise affects the supply voltage V.sub.CC. As one can see in this figure, the impact of the noise at the V.sub.CC supply causes delay in the sense amplifier's response. As the V.sub.CC signal increases due to noise, the reference signal is pulled up, and the array signal is pulled down, the reference signal and the array signal track for approximately 5-10 nanoseconds. This difference in the voltage, seen at the array and reference nodes, generated by the noise event at V.sub.CC causes the crossing of the array signal and the reference signal to be delayed and, thus, the transition of the output OUT of the sense amplifier occurs later. The net result is that the sense amplifier's output response is pushed out by approximately 3 nanoseconds.
One prior art design, conceived to improve in part the above-discussed noise problems, consists in increasing the current gain on the reference side. This can be done by increasing the cascode device in the reference path. A change in size of the cascode device, however, can cause major process, current, and voltage differences between the array side and the reference side. These changes make it very difficult to maximize noise margin, speed balancing, and reference effects across process, voltage, and temperature corners. Consequently, there is a continuing need for improving the common mode noise rejection in pseudo-differential sense amplifiers while maintaining symmetry in the array and reference path, thereby maximizing noise margin, speed balancing, and reference effects across process, voltage, and temperature corners.